The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of composite dielectric material layers in semiconductor devices.
Fabrication of semiconductor devices, such as a metal-oxide-semiconductor (MOS) integrated circuit, involves numerous processing steps. In a semiconductor device, a gate dielectric, typically formed from silicon dioxide (xe2x80x9coxidexe2x80x9d), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many present processes employ features, such as gate conductors and interconnects, which have less than 0.18 xcexcm critical dimension. As feature sizes continue to decrease, the size of the resulting transistor as well as the interconnect between transistors also decreases. Fabrication of smaller transistors allows more transistors to be placed on a single die, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
As MOSFET feature sizes decrease, gate oxide thickness decreases as well. This decrease in gate oxide thickness is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts.
As a result of the continuing decrease in feature size, gate oxide thickness has been reduced so much that oxides are approaching thicknesses below ten angstroms (xc3x85). Unfortunately, thin oxide films may break down when subjected to an electric field, particularly for gate oxides less than 20 xc3x85 thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such a thin gate oxide by a quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that some of these electrons may become entrapped within the gate oxide by, e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, the threshold voltage VT may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of gate voltage, as a result of defects in the gate oxide. Such defects are unfortunately more pronounced in relatively thin gate oxides, since any given defect is more likely to have an adverse effect on the function of the gate oxide. For example, a thin gate oxide may contain pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice. Such unevenness is tolerable at greater thicknesses, but is less so in very thin gate oxides.
A more promising approach to solve the problem of thin gate oxides is to increase the permittivity of the gate dielectric. Permittivity, ∈, of a material reflects the ability of the material to be polarized by an electric field. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, ∈0. Hence, the relative permittivity, referred to as the dielectric constant, of a material is defined as:
K=∈/∈0
While silicon dioxide (sometimes simply referred to as xe2x80x9coxidexe2x80x9d) has a dielectric constant of approximately 4, other dielectric materials have higher K values. Silicon nitride (xe2x80x9cnitridexe2x80x9d), for example, has a K of about 6 to 9 (depending on formation conditions). Much higher K values of, for example, 20 or more can be obtained with various transition metal oxides including hafnium oxide (HfO2), zirconium oxide, (ZrO2), tantalum oxide (Ta2O5), barium strontium titanate (xe2x80x9cBSTxe2x80x9d), lead zirconate titanate (xe2x80x9cPZTxe2x80x9d), and others described more fully below. Using a high-K dielectric material for a gate dielectric would allow a low electrical thickness gate oxide thickness to be achieved even with a physically thick dielectric layer. For example, a high-K gate dielectric with a K of 40 and a thickness of 100 angstroms is substantially electrically equivalent to a silicon dioxide gate dielectric (K about 4) having a thickness of about 10 angstroms. The electrically equivalent thickness of high-K materials may be referred to in terms of the equivalent oxide thickness. Thus, the high-K gate dielectric having a K value of 40 and a given physical thickness has an equivalent oxide thickness which is approximately {fraction (1/10)} the given physical thickness. For higher-K dielectric materials, thicker gate dielectric layers can be formed while maintaining equivalent oxide thickness values lower than are possible with very thin oxide layers. In this way, the reliability problems associated with very thin dielectric layers may be avoided while transistor performance is increased.
One problem which has been reported relating to integration of high-K dielectric materials is unwanted oxidation of silicon by high-K dielectric materials when the high-K dielectric material is formed directly on a silicon substrate. Additionally, in fabricating semiconductor devices having a plurality of layers of dielectric material, a number of steps are typically necessary for changing from deposition of one dielectric material to another in forming successive layers of the plurality of layers. Each of these steps may be accompanied by a heat/cool cycle. Typically, the heat/cool cycles account for as much as 70% of the time required for fabrication of such layers.
Thus, a method of forming a dielectric material, which either overcomes or takes advantage of such reactions, or both, and which provides a simple, efficient fabrication of a high-K dielectric material with a minimum number of discrete steps and with a minimum of production time is needed.
The present invention relates to a method of fabricating a semiconductor device, comprising providing a semiconductor substrate; and depositing on the semiconductor substrate a composite dielectric material layer comprising elements of at least two dielectric materials, in which the step of depositing comprises providing a first precursor for a first dielectric material at a first rate and providing a second precursor for a second dielectric material at a second rate.
In one embodiment, the present invention relates to a method of fabricating a semiconductor device, including providing a semiconductor substrate; and depositing by CVD over the semiconductor substrate a composite dielectric material layer including elements of at least one high-K dielectric material and at least one standard-K dielectric material, in which the step of depositing comprises providing a high-K precursor at a first rate and a standard-K precursor at a second rate and varying at least one of the first rate or the second rate, in which at least a portion of the at least two dielectric materials are deposited simultaneously. As a result of the deposition process, the composite dielectric material layer includes a concentration gradient of the first dielectric material relative to the second dielectric material in a thickness direction of the composite dielectric material layer.
The present invention further relates to a semiconductor device, comprising a semiconductor substrate; and a composite dielectric material layer having a thickness, the composite dielectric material layer comprising elements of a first dielectric material and a second dielectric material, wherein the composite dielectric material layer comprises a varying concentration ratio of the first dielectric material to the second dielectric material through the thickness.
The present invention provides a more efficient method of fabricating a composite dielectric layer, compared to a method in which discrete layers of a first dielectric material and a second dielectric material are deposited, followed by a step of annealing, in which at least a portion of the first and second dielectric materials combine to form a composite dielectric material layer. The present method is more efficient because the steps of depositing the first and second dielectric materials are carried out simultaneously, and no annealing step is needed. Such stepwise deposition of dielectric materials or dielectric precursor materials are disclosed in copending, commonly assigned U.S. patent application Ser. No. 09/977,922, filed Oct. 15, 2001, and U.S. patent application Ser. No. 09/977,928, filed Oct. 15, 2001, and U.S. patent application Ser. No. 10/051,790, (Express Mail No. EF297164362US, entitled PREPARATION OF COMPOSITE HIGH-K/STANDARD-K DIELECTRICS FOR SEMICONDUCTOR DEVICES), filed Jan. 17, 2002, the disclosures of which are hereby incorporated by reference for their teachings with respect to deposition of dielectric materials and precursors thereof. The methods disclosed in these applications include a step of annealing to form a composite dielectric material from stepwise, sequentially deposited sub-layers.
The present invention provides a solution to the problem of forming a high-K dielectric material which both overcomes and takes advantage of previously disfavored reactions between dielectric materials, which requires a minimum number of discrete steps, which avoids stopping and starting and changing from one apparatus or process to another, and which requires significantly less production time. The composite dielectric layer formed may include both a high-K dielectric material and a standard-K dielectric material simultaneously deposited. The method is simple and may be more efficiently carried out. By fabricating the dielectric material layers by simultaneous and continuous deposition of the sub-layers, the intervening heat/cool cycles are avoided. Thus, the present invention addresses and provides a solution for many of the problems of the prior art.